In some conventional computing systems, operations performed by a processor include load/store, hardware prefetch, and arithmetic operations. Load/store is the operation of loading a value from memory (e.g., Synchronous Dynamic Random Access Memory) to a register file or storing a value from a register of a register file to memory. Hardware prefetching is the preloading of data from memory into the register file in order for the data to be ready before being requested. Prefetching reduces the latency associated with memory reads because the processor does not wait for operands to be loaded if they already are preloaded into the register file. An arithmetic operation is an integer operation including, e.g., addition and subtraction between two operands.
In performing a load/store operation, the processor may compute a load/store address. The load/store address is the address of memory from which to load a value to or to which to store a value from the register file. In performing a hardware prefetch, the processor may compute a hardware prefetch address. The hardware prefetch address is the memory address from which data is to be preloaded before being requested for use in a thread execution. In performing an arithmetic operation, the processor may compute an arithmetic operation value, which is the result of an arithmetic operation (e.g., the sum of operand A plus operand B).
The prior art schematic of FIG. 1 illustrates a conventional system 100. As illustrated, the conventional system 100 may include at least three adders (106, 112, and 114) wherein one adder is for computing a load/store address (address generation adder 106), a second adder is for computing a hardware prefetch address (hardware prefetch adder 112), and a third adder is for computing an arithmetic operation value (arithmetic logic unit {ALU} adder 114). Referring to FIG. 1, the address generation adder 106 in computing a load/store address may receive a memory address operand 102 from the register file and an immediate operand 104 (e.g., a constant). An immediate operand may be a constant value listed by an operand of the operation, instead of the operand listing an address.
The adder 106 sums the memory address operand 102 and the immediate operand 104 to create the load/store address, which is sent to multiplexer 108. If a load/store operation is performed, then the multiplexer 108 sends the load/store address to multiplexer 110. On the other hand, if an arithmetic operation is being performed, then the multiplexer 108 may forward a first ALU operand 102 from the register file to the ALU adder 114 instead of forwarding the load/store address to multiplexer 108. If a hardware prefetch is to be performed in addition to or alternative to performing a load/store operation, the multiplexer 108 may forward the load/store address from the address generation adder 106 to the hardware prefetch adder 112 in order to determine a hardware prefetch address.
As illustrated in the schematic of FIG. 1, the hardware prefetch adder 112 is further configured to determine a post increment address. A post increment address is an address equaling a memory address used in a previous execution cycle plus a constant. For example, after or during execution of an operation in a current execution cycle, the address pointing, directly or indirectly, to an operand of the operation may be incremented by a constant to result in the post increment address. The post increment address may point, directly or indirectly, to an operand of an operation to be processed in a subsequent execution cycle.
In the schematic of FIG. 1, adder 112 determines a post increment address by adding the load/store address and the output of multiplexer 116, which selects the post increment constant (pconstant) 118 when computing a post increment address. The pconstant 118 may be predefined and/or hardwired or stored by the system 100. When adder 112 determines a hardware prefetch address, then the multiplexer 116 selects between a hardware prefetch decrement address 120 and a hardware prefetch increment address 122 with which to increment or decrement the load/store address. Adder 112 outputs the post increment address or hardware prefetch address 124, which may be sent to a register file the current execution cycle or the input of multiplexer 110 the next execution cycle. The hardware prefetch address 124 inputted to multiplexer 110 the next execution cycle may be used to access the data cache 136 for prefetching a value at the memory address 134. Hence, multiplexer 110 selects between the load/store address of a current execution cycle and the hardware prefetch address of the previous execution cycle depending on whether a load/store operation or a hardware prefetch is being performed.
If an arithmetic operation is to be computed, in addition to multiplexer 108 sending a first ALU operand 102 to the input of ALU adder 114, multiplexer 126 sends an output selected from a second ALU operand 128 from the register file and an Immediate ALU operand 130 (i.e., a constant) depending on the arithmetic operation. For example, an arithmetic operation may add two values stored in the register files. Hence, the input operands of the instruction may point to two registers of the register file storing the values to be added. In another example, one operand may point to a value stored in the register file while the other operand lists a predefined constant. The adder 114 then adds the output of multiplexer 126 and the ALU first operand 102 to output an arithmetic operation value 132.
One problem with system 100 is that three adders are required to process the operations, thus increasing area of the circuitry and power consumption of the processor.